Microsoft KB Archive/34774

= FIX: FWAIT Prefixes Generated for Processor Control Instructions =

Article ID: 34774

Article Last Modified on 10/29/2003

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APPLIES TO


 * Microsoft Macro Assembler 5.1 Standard Edition
 * Microsoft Macro Assembler 5.1a

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This article was previously published under Q34774



SYMPTOMS
For a 80287 or 80387 processor, MASM should not be generating FWAIT prefixes for processor control instructions that do not have no-wait forms, including the following:   FLDCW, FLDENV, FRSTOR, FINCSTP, FDECSTP, FFREE, and FNOP



STATUS
Microsoft has confirmed this to be problem in MASM versions 5.10 and 5.10a. This problem was corrected in MASM version 6.00.



MORE INFORMATION
The following is an example of the wait incorrectly generated by MASM for the FLDCW instruction. The fldcw generates the opcodes &quot;9B D9 2D&quot; when it should only generate &quot;D9 2D&quot; without the &quot;9B&quot; wait.

Sample Code
; Assemble options needed: none

.386  .387   .model small .data

d1 DW 0

.code fldcw d1

END

Additional query words: 5.10 buglist5.10 buglist5.10a fixlist6.00

Keywords: kbfix KB34774

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